Fast principal component analysis based on hardware architecture of generalized Hebbian algorithm

Authors:
Shiow-Jyu Lin;Yi-Tsan Hung;Wen-Jyi Hwang
Affiliations:
Department of Computer Science and Information Engineering, National Taiwan Normal University, Taipei, Taiwan and Department of Electronic Engineering, National Ilan University, I-Lan, Taiwan;Department of Computer Science and Information Engineering, National Taiwan Normal University, Taipei, Taiwan;Department of Computer Science and Information Engineering, National Taiwan Normal University, Taipei, Taiwan
Venue:
ISICA'10 Proceedings of the 5th international conference on Advances in computation and intelligence
Year:
2010

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Abstract

This paper presents a novel hardware architecture for fast principle component analysis (PCA). The architecture is developed based on generalized Hebbian algorithm (GHA). In the architecture, the updating of different synaptic weight vectors are divided into a number of stages. The results of precedent stages are used for the computation of subsequent stages for expediting training speed and lowering the area cost. The proposed architecture has been embedded in a systemon-programmable-chip (SOPC) platform for physical performance measurement. Experimental results show that the proposed architecture is an effective alternative for fast PCA in attaining both high performance and low computation time.