Practical Bounded-Skew Clock Routing
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
A parallel algorithm for zero skew clock tree routing
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Routing tree topology construction to meet interconnect timing constraints
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Computing the Shortest Network under a Fixed Topology
IEEE Transactions on Computers
Efficient octilinear Steiner tree construction based on spanning graphs
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Circuit-simulated obstacle-aware Steiner routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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