International Journal of Reconfigurable Computing - Special issue on Selected Papers from the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2011)
SURF algorithm in FPGA: a novel architecture for high demanding industrial applications
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
FPGA-based module for SURF extraction
Machine Vision and Applications
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In this paper, we propose a novel architecture to accelerate the Speeded Up Robust Features (SURF) algorithm by the use of configurable hardware. SURF is used in optical tracking systems to robustly detect distinguishable features within an image in a scale and rotation invariant way. In its performance critical part, SURF computes convolution filters at multiple scale levels without the need to create down-sampled versions of the original image. However, the algorithm exposes a very irregular memory access pattern. We designed a configurable and scalable architecture to overcome these memory access issues without the need to use any internal block RAM resources of the FPGA. The complete detector and descriptor stage of SURF has been implemented and validated in a Virtex 5 FPGA.