A 10-Gb/s inductorless transimpedance amplifier

Authors:
Omeed Momeni;Hossein Hashemi;Ehsan Afshari
Affiliations:
Department of Electrical and Computer Engineering, Cornell University, Ithaca, NY;Department of Electrical Engineering, University of Southern California, Los Angeles, CA;Department of Electrical and Computer Engineering, Cornell University, Ithaca, NY
Venue:
IEEE Transactions on Circuits and Systems II: Express Briefs
Year:
2010

Citing 3
Cited 4

Design of Integrated Circuits for Optical Communications

Design of Integrated Circuits for Optical Communications
A 20-Gb/s transformer-based current-mode optical receiver in 0.13-µm CMOS

IEEE Transactions on Circuits and Systems II: Express Briefs
The transimpedance limit

IEEE Transactions on Circuits and Systems Part I: Regular Papers

On the use of multi-path inductorless TIAs for larger transimpedance limit

Analog Integrated Circuits and Signal Processing
On the use of multi-path inductorless TIAs for larger transimpedance limit

Analog Integrated Circuits and Signal Processing
Low-power 10 Gb/s inductorless inverter based common-drain active feedback transimpedance amplifier in 40 nm CMOS

Analog Integrated Circuits and Signal Processing
8 Gbits/s inductorless transimpedance amplifier in 90 nm CMOS technology

Analog Integrated Circuits and Signal Processing

Quantified Score

Hi-index	0.00

Visualization

Abstract

A new technique to design an inductorless transimpedance amplifier (TIA) is introduced. This technique uses N similar TIAs in parallel configuration to boost the overall bandwidth while keeping the transimpedance gain constant. Using this method, we design and implement a 10-Gb/s inductorless TIA with an active area of only 0.06 mm2 and a differential transimpedance gain of 62 dBΩ in a digital 0.13-µm CMOS process. There is good agreement among the theory, simulation, and experimental results.