Thread Synchronization Unit (TSU): A Building Block for High Performance Computers
ISHPC '97 Proceedings of the International Symposium on High Performance Computing
First version of a data flow procedure language
Programming Symposium, Proceedings Colloque sur la Programmation
Introduction to the cell multiprocessor
IBM Journal of Research and Development - POWER5 and packaging
Data-Driven Multithreading Using Conventional Microprocessors
IEEE Transactions on Parallel and Distributed Systems
Sequoia: programming the memory hierarchy
Proceedings of the 2006 ACM/IEEE conference on Supercomputing
CellSs: a programming model for the cell BE architecture
Proceedings of the 2006 ACM/IEEE conference on Supercomputing
Sequoia: programming the memory hierarchy
Proceedings of the 2006 ACM/IEEE conference on Supercomputing
Computer
A Practical Data Flow Computer
Computer
CellSs: making it easier to program the cell broadband engine processor
IBM Journal of Research and Development
Orchestrating data transfer for the cell/B.E. processor
Proceedings of the 22nd annual international conference on Supercomputing
TFlux: A Portable Platform for Data-Driven Multithreading on Commodity Multicore Systems
ICPP '08 Proceedings of the 2008 37th International Conference on Parallel Processing
Hybrid access-specific software cache techniques for the cell BE architecture
Proceedings of the 17th international conference on Parallel architectures and compilation techniques
Declarative aspects of memory management in the concurrent collections parallel programming model
Proceedings of the 4th workshop on Declarative aspects of multicore programming
Mapping and Synchronizing Streaming Applications on Cell Processors
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
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In this paper we present the Data-Driven Multithreading Virtual Machine for the Cell Processor (DDM-VMc). Data-Driven Multithreading is a non-blocking multithreading model that decouples the synchronization from the computation portions of a program allowing them to execute asynchronously in a data-flow manner. The core of the DDM model is the Thread Scheduling Unit (TSU), which schedules threads dynamically at runtime based on data availability. DDM-VMc implements the TSU as a software module running on the PPE core of the Cell, allowing the SPE cores to execute the program threads. DDM-VMc virtualizes the parallel resources of the Cell, handles the heterogeneity of the cores and manages the Cell memory hierarchy efficiently. We present the architecture of DDM-VMc and provide an in-depth performance analysis using a suite of standard computational benchmarks. The evaluation shows that DDM-VMc scales well and tolerates scheduling overheads and memory latencies effectively. Furthermore, DDM-VMc compares favorably with other platforms targeting the Cell processor.