A high-throughput hardware architecture for the H.264/AVC half-pixel motion estimation targeting high-definition videos

Authors:
Marcel M. Corrêa;Mateus T. Schoenknecht;Robson S. Dornelles;Luciano V. Agostini
Affiliations:
Federal University of Pelotas, Pelotas, RS, Brazil;Federal University of Pelotas, Pelotas, RS, Brazil;Federal University of Pelotas, Pelotas, RS, Brazil;Federal University of Pelotas, Pelotas, RS, Brazil
Venue:
International Journal of Reconfigurable Computing - Special issue on selected papers from the southern programmable logic conference (SPL2010)
Year:
2011

Citing 3
Cited 1

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Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation
An Efficient Hardware Architecture for Quarter-Pixel Accurate H.264 Motion Estimation

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Analysis and design of a context adaptable SAD/MSE architecture

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DMPDS: a fast motion estimation algorithm targeting high resolution videos and its FPGA implementation

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Abstract

This paper presents a high-performance hardware architecture for the H.264/AVC Half-Pixel Motion Estimation that targets high-definition videos. This design can process very high-definition videos like QHDTV (3840 × 2048) in real time (30 frames per second). It also presents an optimized arrangement of interpolated samples, which is the main key to achieve an efficient search. The interpolation process is interleaved with the SAD calculation and comparison, allowing the high throughput. The architecture was fully described in VHDL, synthesized for two different Xilinx FPGA devices, and it achieved very good results when compared to related works.