Assessing and optimizing microarchitectural performance of event processing systems

  • Authors:

  • Marcelo R. N.Mendes;Pedro Bizarro;Paulo Marques

  • Affiliations:

  • CISUC, University of Coimbra, Dep. Eng. Informática - Pólo II, Coimbra, Portugal;CISUC, University of Coimbra, Dep. Eng. Informática - Pólo II, Coimbra, Portugal;CISUC, University of Coimbra, Dep. Eng. Informática - Pólo II, Coimbra, Portugal

  • Venue:
  • TPCTC'10 Proceedings of the Second TPC technology conference on Performance evaluation, measurement and characterization of complex systems
  • Year:
  • 2010

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Abstract

Event Processing (EP) systems are being progressively used in business critical applications in domains such as algorithmic trading, supply chain management, production monitoring, or fraud detection. To deal with high throughput and low response time requirements, these EP systems mainly use the CPU-RAM sub-system for data processing. However, as we show here, collected statistics on CPU usage or on CPU-RAM communication reveal that available systems are poorly optimized and grossly waste resources. In this paper we quantify some of these inefficiencies and propose cache-aware algorithms and changes on internal data structures to overcome them. We test the before and after system both at the microarchitecture and application level and show that: i) the changes improve microarchitecture metrics such as clocks-per-instruction, cache misses or TLB misses; ii) and that some of these improvements result in very high application level improvements such as a 44% improvement on stream-to-table joins with 6-fold reduction on memory consumption, and order-of-magnitude increase on throughput for moving aggregation operations.