Design and implementation of an ordered memory access architecture

Authors:
S. Sriram;E. A. Lee
Affiliations:
EECS Department, UC Berkeley, Berkeley, CA;EECS Department, UC Berkeley, Berkeley, CA
Venue:
ICASSP'93 Proceedings of the 1993 IEEE international conference on Acoustics, speech, and signal processing: plenary, special, audio, underwater acoustics, VLSI, neural networks - Volume I
Year:
1993

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Abstract

This paper describes a multiprocessor machine for realtime Digital Signal Processing that uses commercial programmable DSP chps. The archtecture is a shared memory, single shared bus parallel processor designed to run signal processing tasks that can be statically scheduled. The design is based on the archtecture proposed in [1]. A prototype has since been built. The implementation details and performance results are discussed here.