An area-efficient path memory structure for VLSI implementation of high speed Viterbi decoders
Integration, the VLSI Journal
Parallel high-throughput limited search trellis decoder VLSI design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the eighth ACM/IEEE symposium on Architectures for networking and communications systems
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A new approach to survivor path architectures for Viterbi decoders is proposed based on hybrid architectures that combine the classical register-exchange and trace-back methods. Two classes of hybrid architecture are proposed the hybrid pretrace-back architecture and the hybrid trace-forward architecture. Pretrace-back is a preprocessing of the add-compare-select (ACS) decisions to increase the effective trace-back recursion rate, while trace-forward is a concurrent processing of the decisions to initialize the trace-back recursion. Both of these architectures can be implemented using a single compact memory, typically twice the survivor path length in size, without any loss in throughput compared to conventional traceback architectures. Based on area estimates for common decoding problems the hybrid architectures reduce the required chip area by up to 40% compared with the popular k-pointer traceback architecture.