A 4.32 mm2 170mW LDPC decoder in 0.13μm CMOS for WiMax/Wi-Fi applications

Authors:
Dan Bao;Chuan Wu;Yan Ying;Yun Chen;Xiao Yang Zeng
Affiliations:
Fudan University, Shanghai, China;Fudan University, Shanghai, China;Fudan University, Shanghai, China;Fudan University, Shanghai, China;Fudan University, Shanghai, China
Venue:
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Year:
2011

Citing 2
Cited 0

Software-Defined Radio Prospects for Multistandard Mobile Phones

Computer
Programmable architecture for flexi-mode QC-LDPC decoder supporting wireless LAN/MAN applications and beyond

IEEE Transactions on Circuits and Systems Part I: Regular Papers

Quantified Score

Hi-index	0.00

Visualization

Abstract

An energy-efficient programmable LDPC decoder is proposed for WiMax and Wi-Fi applications. The proposed decoder is designed with overlapped processing units, flexible message passing network and medium-grain partitioned memories to achieve flexibility, area reduction, and energy efficiency. The decoder can be programmed by host processor with several special-purpose micro-instructions. Thus, various operation modes can be reconfigured. Fabricated in SMIC 0.13μm 1P8M CMOS process, the chip occupies 4.32 mm2 with core area 2.97 mm2, and consumes 170mW with a throughput of 302Mb/s when operating at 145MHz and 1.2V.