Formal methods in circuit design

Authors:
V. Stavridou
Affiliations:
Royal Holloway and Bedford New College, London, UK
Venue:
Formal methods in circuit design
Year:
1993

Citing 0
Cited 3

Towards verifying VHDL descriptions of processors

EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
An Object-Oriented Framework for the Formal Verification of Processors

ECOOP '95 Proceedings of the 9th European Conference on Object-Oriented Programming
Synchronous digital circuits as functional programs

ACM Computing Surveys (CSUR)

Quantified Score

Hi-index	0.00

Visualization

Abstract