Compact yet high performance (CyHP) library for short time-to-market with new technologies
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Large Standard Cell Libraries and Their Impact on Layout Area and Circuit Performanc
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
An evolutionary approach for standard-cell library reduction
Proceedings of the 17th ACM Great Lakes symposium on VLSI
FreePDK: An Open-Source Variation-Aware Design Kit
MSE '07 Proceedings of the 2007 IEEE International Conference on Microelectronic Systems Education
On the decreasing significance of large standard cells in technology mapping
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A Fast Heuristic for Extending Standard Cell Libraries with Regular Macro Cells
ISVLSI '10 Proceedings of the 2010 IEEE Annual Symposium on VLSI
| Hi-index | 0.00 |
Current EDA tools are often based on standard-cell libraries for the design of modern complex systems-on-chip. In general, there are opposite trends to compact and extend the standard cell libraries, and to move towards custom libraries, highly optimized for specific goals (e.g., area, timing or power consumption) or designs. We thus propose a design methodology for library sizing that combines decimation strategies and generation of cell variants. The proposed methodology is based on Simulated Annealing, also integrating heuristic principles to efficiently guide the exploration process. The approach has been validated on a set of common benchmarks for logic synthesis, demonstrating interesting results, specially when starting from a relative small initial library.