Parametric fault model for RTD based threshold logic gates

Authors:
Manoj Kumar Goparaju;Spyros Tragoudas
Affiliations:
Department of Electrical and Computer Engineering, Southern Illinois University Carbondale, Carbondale, IL;Department of Electrical and Computer Engineering, Southern Illinois University Carbondale, Carbondale, IL
Venue:
ICC'06 Proceedings of the 10th WSEAS international conference on Circuits
Year:
2006

Citing 4
Cited 0

Parallel Adder Design with Reduced Circuit Complexity Using Resonant Tunneling Transistors and Threshold Logic

Analog Integrated Circuits and Signal Processing - Special issue on analog nano-electronics
Switching and Finite Automata Theory: Computer Science Series

Switching and Finite Automata Theory: Computer Science Series
An Automatic Test Pattern Generation Framework for Combinational Threshold Logic Networks

ICCD '04 Proceedings of the IEEE International Conference on Computer Design
A note on single-processor scheduling with time-dependent execution times

Operations Research Letters

Quantified Score

Hi-index	0.00

Visualization

Abstract

One of major implementations of Linear Threshold Gate (LTG) is via resonant tunneling diodes (RTD). The functionality of this threshold logic gate greatly depends on the parameters of the RTD and parametric faults impact its functionality. A suitable fault model for Combinational Threshold Logic gates is presented. A methodology is also developed to generate test patterns that detect these parametric faults.