Chip level charge recovery

  • Authors:
  • Ashish Kumar;Vivek Asthana

  • Affiliations:
  • Non-Volatile Static Memories Group, STMicroelectronics Pvt. Ltd., Greater Noida, UP, India;Non-Volatile Static Memories Group, STMicroelectronics Pvt. Ltd., Greater Noida, UP, India

  • Venue:
  • ICC'06 Proceedings of the 10th WSEAS international conference on Circuits
  • Year:
  • 2006

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Abstract

Charge recovery uses charge from falling datalines to charge the rising datalines. Previous works addresses to this phenomena using statistical switching models where the amount of energy savings depends on the number of lines shorted, the control circuitry, data length & pattern [1]. We are extending the concept to creation of an intermediate level virtual source/sink, which acts as a charge reservoir & facilitates for charge recovery. Implementation of the concept provides feasibility for chip level charge recovery, even suitable for a single switching line. We could observe up to 35% reduction in switching power.