RF microelectronics
Design of a 1 V Low Power 900 MHz QVCO
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
| Hi-index | 0.00 |
A 1-V 2.4/4.8-GHz 4.59 mW Quadrature Voltage Controlled Oscillator (QVCO) has been designed in 0.18 μm CMOS technology. All-pMOS VCO followed by static frequency divider using source degeneration based D flip-flops is proposed. An accurate small signal analysis model of proposed D flip-flops is provided to estimate the maximum operating frequency of the divider. The advantages of proposed QVCO are analyzed in terms of phase noise and suppress the higher order (≥3) harmonics through linearization. The best overall performance is displayed by the inversion mode pMOS varactor. The proposed QVCO is tuned from 2.4 to 2.5 GHz with a tuning voltage varying from 0 to 1 V, additional 80 MHz increased by switched capacitor array (SCA). Compared to the conventional QVCO without resistor, the proposed QVCO shows good 1/f3 close-in phase noise. The simulated results shows about 6.0 dB, 8.0 dB, 6.0 dB and 0 dB of phase noise improvement at 10 KHz, 100 KHz, 1 MHz and 3 MHz offset frequency from a 2.4 GHz carrier. The input sensitivity of the proposed divider is simulated from 50 mV to 510 mV to achieve the operating frequency varies from 3.0 GHz to 6.2 GHz. The 3rd harmonic distortion is 44 dB less than that of fundamental frequency.