Design of a 1 V Low Power 900 MHz QVCO

Authors:
Prabir K. Saha;Ashudeb Dutta;A. Patra;T. K. Bhattacharyya
Affiliations:
Indian Institute of Technology - Kharagpur;Indian Institute of Technology - Kharagpur;Indian Institute of Technology - Kharagpur;Indian Institute of Technology - Kharagpur
Venue:
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Year:
2006

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Design of 1 V CMOS VCO followed by proposed source degeneration based CML flip-flops for 2.4 GHz short range wireless applications

Proceedings of the International Conference & Workshop on Emerging Trends in Technology

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Abstract

This paper describes the design of a 1V, 900 MHz Quadrature Voltage Controlled Oscillator (QVCO) implemented in 0.18µm CMOS technology. The VCO can be tuned from 825 to 975 MHz, which corresponds to a tuning range of 16.6%, consuming only 3.5 mW of power for quadrature signal outputs. The phase noise of the VCO is -136 dBc/Hz at 3 MHz offset from 900 MHz. The VCO features discrete tuning using switched capacitors with a Kvco of 50 MHz/V which makes it very suitable for using in a PLL. Challenges with low voltage implementation of the VCO and modifications required both at device and circuit level are discussed in detail. Novel design of the VCO has also ensured very low supply sensitivity of the output frequency (KVDD=6 MHz/V) despite low supply voltage.