CMOS Circuit Design, Layout, and Simulation, Second Edition
CMOS Circuit Design, Layout, and Simulation, Second Edition
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
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A PLL is a negative feedback system where an oscillator-generated output signal is phase and frequency locked to a reference signal. A 5GHz PLL based frequency synthesizer is presented in this paper. The proposed PLL is designed using 90nm CMOS technology with 1.8V power supply. A phase lock loop (PLL) is a control system which involves negative feedback, and generates a signal that has a fixed relation to the phase of a "reference" signal. This circuit responds to both the frequency and the phase of the input signals, automatically raising or lowering the frequency of a controlled oscillator until it is matched to the reference in both frequency and phase. Since a single integrated circuit can provide a complete phase-locked-loop building block, the technique is widely used in modern electronic devices, with output frequencies from a fraction of a cycle per second up to many gigahertzes. The software being used is spice engine and waveform viewer.