EXPRESSION: a language for architecture exploration through compiler/simulator retargetability
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Principles of Functional Verification
Principles of Functional Verification
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Interrupt behaviors, particularly the external ones, are difficult to verify in a microprocessor. Because the external interrupt arrival time and the microprocessor response time must be precise, verification requires sophisticated hardware and software design. This paper proposes a computer-aided design tool, called processor exception verification tool (PEVT), to verify the external interrupt behaviors of microprocessors, including individual, multiple, and nested interrupts. An architecture description language extension, called Exception Description Language (EXPDL), is developed for the designer capture the external interrupt behaviors for the microprocessor under verification. PEVT is responsible for generating the verification cases, consisting of both the hardware and software modules, which are then used to trigger the expected behaviors. A monitor is also generated from the EXPDL description to verify these cases.