A parallel packet switch architecture with input-output-queued switches and buffering in the demultiplexors

  • Authors:

  • Yi Dai;Zhi-Gang Sun;Jin-Shu Su

  • Affiliations:

  • Institute of Network and Information Security, National University of Defense Technology, Changsha, Hunan, China;Institute of Network and Information Security, National University of Defense Technology, Changsha, Hunan, China;Institute of Network and Information Security, National University of Defense Technology, Changsha, Hunan, China

  • Venue:
  • ICCOM'06 Proceedings of the 10th WSEAS international conference on Communications
  • Year:
  • 2006

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Abstract

A packet switch with parallel switching planes is a parallel packet switch (PPS). A PPS can scale-up to larger aggregate capacity and faster line speeds than can a single plane. It is an open problem to design a PPS that is feasible to implement using multiple lower speed packet switches. Many solutions proposed previously are essentially impractical because of high communication complexity. In this paper, we present a high performance PPS architecture by using a small fixed-size buffer in the demultiplexor and by applying the same matching at each of the k parallel CIOQ switches during each cell slot. Our scheme guarantees a way for cells of a flow to be read in order from the output queues of the switches, thus, eliminating the need for cell reordering in multiplexor. Each multiplexor only need to deliver cells from the output queues of the k parallel switch planes in round robin manner, and little state information easily obtained by the scheduler is communicated to the multiplexors. Our work in this paper reduces the communication overhead considerably and makes the PPS more practical to implement compared to other PPS designs.