Dynamically-Allocated Multi-Queue Buffers for VLSI Communication Switches
IEEE Transactions on Computers
Scheduling algorithms for input-queued cell switches
Scheduling algorithms for input-queued cell switches
WSC '96 Proceedings of the 28th conference on Winter simulation
A quantitive comparision of iterative scheduling algoithm for input-queued switches
Computer Networks and ISDN Systems
The iSLIP scheduling algorithm for input-queued switches
IEEE/ACM Transactions on Networking (TON)
Packet reordering is not pathological network behavior
IEEE/ACM Transactions on Networking (TON)
Switching using parallel input-output queued switches with no speedup
IEEE/ACM Transactions on Networking (TON)
Parallel Packet Switching Using Multiplexors with Virtual Input Queues
LCN '02 Proceedings of the 27th Annual IEEE Conference on Local Computer Networks
Analysis of the parallel packet switch architecture
IEEE/ACM Transactions on Networking (TON)
Load balanced Birkhoff-von Neumann switches, part II: multi-stage buffering
Computer Communications
Load balanced Birkhoff-von Neumann switches, part I: one-stage buffering
Computer Communications
Overall Blocking Behavior Analysis of General Banyan-Based Optical Switching Networks
IEEE Transactions on Parallel and Distributed Systems
A coordination scheduling mechanism to guarantee packet ordering in parallel packet switch
International Journal of Electronic Security and Digital Forensics
ICCOM'06 Proceedings of the 10th WSEAS international conference on Communications
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A packet switch with parallel switching planes is a parallel packet switch (PPS). A PPS can scale-up to faster line speeds than can a single-plane switch. It is an open problem to design a PPS that is feasible to implement using existing low-cost hardware components where no component runs faster than line speed. A PPS must be able to internally load balance traffic, have packet delays comparable to a reference single-plane switch, and provide QoS (bandwidth, delay, and loss guarantees) to flows. We investigate a new architecture for a PPS that uses virtual input queues (VIQ) in the output multiplexors to achieve packet-level load balancing. A VIQ at an output multiplexor consists of one FIFO queue for each input. For K planes and N ports, our VIQ PPS requires KN cells of buffering in the input demultiplexors and 2NK+2K cells of buffering in the output multiplexors to achieve guaranteed loss-free operation and in-order cell delivery. Using simulation models, the new VIQ PPS is shown to offer improved delay performance compared to existing PPS designs. For balanced and unbalanced loads the VIQ PPS is stable where a reference iSLIP single-plane switch is unstable.