Exploiting time predictable two-level scratchpad memory for real-time systems

Authors:
Yu Liu;Wei Zhang
Affiliations:
Southern Illinois University Carbondale, Carbondale, IL;Virginia Commonwealth University, Richmond, VA
Venue:
Proceedings of the 2011 ACM Symposium on Applied Computing
Year:
2011

Citing 2
Cited 0

An optimal memory allocation scheme for scratch-pad-based embedded systems

ACM Transactions on Embedded Computing Systems (TECS)
Assigning Program and Data Objects to Scratchpad for Energy Reduction

Proceedings of the conference on Design, automation and test in Europe

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Abstract

In modern computer architectures, caches are time unpredictable, and thus can significantly increase the complexity of worse-case execution time (WCET) analysis for real-time systems. This paper proposes a time predictable two-level scratchpad (SPM) based architecture for VLIW (Very Long Instruction Word) processors, and an ILP (Integer Linear Programming) based static memory objects assignment algorithm is utilized in order not to harm the time predictability of SPMs. Also, both the timing and energy performance of our two-level SPM based architecture are completely evaluated in this paper. Our experimental results indicate that the timing and energy performance of our architecture is superior to the similar cache based architecture for 75% of the benchmarks we studied.