Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Parsing Languages by Pattern Matching
IEEE Transactions on Software Engineering
Programming language theory and its implementation
Programming language theory and its implementation
Algebraic construction of compilers
Theoretical Computer Science
Implementation of CTL model checker update
ICCOMP'07 Proceedings of the 11th WSEAS International Conference on Computers
Hi-index | 0.00 |
In this work, is presented the methodology and supporting sets of tools, what permitted the possibility automatically generate of the algorithms verify the models for temporal logics from a set of algebraic specifications. This fact is of great deal to the research of suggested aim. The development of temporal logics and the model checking the algorithms can be used to the verification property of system. These are used in to specify model checkers as the mappings of the form MC: Ls → Lt where Ls is a temporal logic source language and Lt is a target language represents sets a state of the model M as MC (f∈Ls) ={s∈M| s|=f}. Is noticed how this algebraic framework can be used to specify of the model checking algorithms for CTL (Computation Tree Logic). The paper [10] is the base of results obtained.