Interpreter instruction scheduling

Authors:
Stefan Brunthaler
Affiliations:
Institut für Computersprachen, Technische Universität Wien, Wien
Venue:
CC'11/ETAPS'11 Proceedings of the 20th international conference on Compiler construction: part of the joint European conferences on theory and practice of software
Year:
2011

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Abstract

Whenever we extend the instruction set of an interpreter, we risk increased instruction cache miss penalties.We can alleviate this problem by selecting instructions from the instruction set and rearranging them such that frequent instruction sequences are co-located in memory. We take these frequent instruction sequences from hot program traces of external programs and we report a maximum speedup by a factor of 1.142. Thus, interpreter instruction scheduling complements the improved efficiency of an extended instruction set by optimizing its instruction arrangement.