Code arrangement of embedded java virtual machine for NAND flash memory

Authors:
Chun-Chieh Lin;Chuen-Liang Chen
Affiliations:
Department of Computer Science and Information Engineering, National Taiwan University, Taipei, Taiwan;Department of Computer Science and Information Engineering, National Taiwan University, Taipei, Taiwan
Venue:
HiPEAC'08 Proceedings of the 3rd international conference on High performance embedded architectures and compilers
Year:
2008

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Abstract

This paper proposed a systematic approach to optimize J2ME KVM running directly on NAND flash memories (XIP). The refined KVM generated cache misses 96% less than the original version did. The approach appended a post processor to the compiler. The post processor relocates and rewrites basic blocks within the VM interpreter using a unique mathematical model. This approach analyzed not only static control flow graph but also the pattern of bytecode instruction streams, since we found the input sequence drives the program flow of the VM interpreter. The proposed mathematical model is used to express the execution flows of Java instructions of real applications. Furthermore, we concluded the mathematical model is a kind of graph partition problem, and this finding helped the relocation process to move program blocks to proper NAND flash pages. The refinement approach dramatically improved the locality of the virtual machine thus reduced cache miss rates. Our technique can help J2ME-enabled devices to run faster and extend longer battery life. The approach also brings potential for designers to integrate the XIP function into System-on-Chip thanks to lower demand for cache memory.