Migrating a HoneyDepot to Hardware
SECUREWARE '07 Proceedings of the The International Conference on Emerging Security Information, Systems, and Technologies
FPGA based string matching for network processing applications
Microprocessors & Microsystems
Bitstream Encryption and Authentication Using AES-GCM in Dynamically Reconfigurable Systems
IWSEC '08 Proceedings of the 3rd International Workshop on Security: Advances in Information and Computer Security
FPGA-Based Intrusion Detection System for 10 Gigabit Ethernet
IEICE - Transactions on Information and Systems
Evaluating Intrusion Detection Systems in High Speed Networks
IAS '09 Proceedings of the 2009 Fifth International Conference on Information Assurance and Security - Volume 02
Bitstream relocation with local clock domains for partially reconfigurable FPGAs
Proceedings of the Conference on Design, Automation and Test in Europe
MalCoBox: Designing a 10 Gb/s Malware Collection Honeypot Using Reconfigurable Technology
FPL '10 Proceedings of the 2010 International Conference on Field Programmable Logic and Applications
A Dynamically Reconfigured Network Platform for High-Speed Malware Collection
RECONFIG '10 Proceedings of the 2010 International Conference on Reconfigurable Computing and FPGAs
Malacoda: towards high-level compilation of network security applications on reconfigurable hardware
Proceedings of the eighth ACM/IEEE symposium on Architectures for networking and communications systems
NetStage/DPR: A self-reconfiguring platform for active and passive network security operations
Microprocessors & Microsystems
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Increasing transmission speeds in high-performance networks pose significant challenges to protecting the systems and networking infrastructure. Reconfigurable devices have already been used with great success to implement lower-levels of appropriate security measures (e.g., deep-packet inspection). We present a reconfigurable processing architecture capable of handling even application-level tasks, and also able to autonomously adapt itself to varying traffic patterns using dynamic partial reconfiguration. As a first use-case, we examine the collection of Malware by emulating an entire honeynet of potentially hundreds of thousands of hosts using a single-chip implementation of the architecture.