A Low-Voltage CMOS Exponential Function Circuit for AGC Applications
SBCCI '98 Proceedings of the 11th Brazilian Symposium on Integrated circuit design
A 35 dB-linear exponential function generator for VGA and AGC applications
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-voltage FGMOS based analog building blocks
Microelectronics Journal
Low-voltage CMOS current-mode exponential circuit with 70dB output dynamic range
Microelectronics Journal
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A new CMOS current-mode pseudo-exponential circuit based on the n-order Taylor series expansion will be presented. The most important advantage of the circuit with respect to the previously reported similar ones is the smaller value of the total computing error (under 0.3 dB), for a maximal output range of the proposed function generator greater than 40 dB. The total error could be very easily reduced by increasing the number of terms considered in the Taylor expansion. The circuit also presents the advantage of the independence of the output current on technological parameters. The frequency response is improved due to the strong inversion operation of all MOS transistors and to the current-mode operation of the circuit. The circuit area is relatively small due to the exclusively utilization of MOS transistors. The SPICE simulations confirm the theoretical estimated results. The proposed exponential function generator is designed in 0.12- µm CMOS technology and it consumes a reasonable power (less than 0.3 mW) for obtaining the previous mentioned computing error and has a low-voltage operation (a minimal accepted supply voltage under 1.2 V). The total silicon occupied area of the exponential function generator with third-order approximation is about 5.9 µm × 7.9 µm.