Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
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A high precision low dropout regulator (LDO) with nested feedback loops is proposed in this paper. By nesting a zero-tracking compensation loop inside of the negative feedback loop comprising an error amplifier, the independence of off-chip capacitor and effective series resistance (ESR) is ensured for different load currents and operating voltages. This circuit is designed and fabricated using a 0.35@mm standard CMOS process. The die area is a 1350@mmx560@mm. The measurement results show that the total error of the output voltage caused by line and load variations is less than +/-3% in low quiescent current (Iddq) or low voltage scenarios. Besides, the smallest dropout of the LDO, 0.11V, while the output current is 165mA, the output load is 4.7@mF and 20 in parallel.