45-nm silicon-on-insulator CMOS technology integrating embedded DRAM for high-performance server and ASIC applications

  • Authors:

  • S. S. Iyer;G. Freeman;C. Brodsky;A. I. Chou;D. Corliss;S. H. Jain;N. Lustig;V. McGahay;S. Narasimha;J. Norum;K. A. Nummy;P. Parries;S. Sankaran;C. D. Sheraw;P. R. Varanasi;G. Wang;M. E. Weybright;X. Yu;E. Crabbe;P. Agnello

  • Affiliations:

  • IBM Systems and Technology Group, Hopewell Junction, NY;IBM Systems and Technology Group, Hopewell Junction, NY;IBM Systems and Technology Group, Hopewell Junction, NY;IBM Systems and Technology Group, Hopewell Junction, NY;IBM Systems and Technology Group, Hopewell Junction, NY;IBM Systems and Technology Group, Hopewell Junction, NY;IBM Systems and Technology Group, Hopewell Junction, NY;IBM Systems and Technology Group, Hopewell Junction, NY;IBM Systems and Technology Group, Hopewell Junction, NY;IBM Systems and Technology Group, Hopewell Junction, NY;IBM Systems and Technology Group, Hopewell Junction, NY;IBM Systems and Technology Group, Hopewell Junction, NY;IBM Systems and Technology Group, Hopewell Junction, NY;IBM Systems and Technology Group, Hopewell Junction, NY;IBM Systems and Technology Group, Hopewell Junction, NY;IBM Systems and Technology Group, Hopewell Junction, NY;IBM Systems and Technology Group, Hopewell Junction, NY;IBM Systems and Technology Group, Hopewell Junction, NY;IBM Systems and Technology Group, Hopewell Junction, NY;IBM Systems and Technology Group, Hopewell Junction, NY

  • Venue:
  • IBM Journal of Research and Development
  • Year:
  • 2011

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Abstract

The 45-nm technology, called 12S and developed for IBM POWER7®, is an extremely robust and versatile technology platform that allows for a rich set of features that include embedded dynamic random access memory (DRAM), performance and dense static RAM (SRAM), a trench-based decoupling capacitor, a comprehensive device menu, and a high-performance hierarchical back-end interconnect scheme, all built on a silicon-on-insulator (SOI) substrate. Embedded DRAM was implemented for production in high-performance SOI for the first time and allowed us to leapfrog two generations of conventional SRAM densities. Immersion lithography was also employed for the first time in 45-nm IBM products. Our 45-nm design point represents a judicious leverage of silicon oxynitride dielectrics, scaled device technology, and rich features to yield chip-level performance enhancement of more than 50%, compared with our 65-nm node at comparable or less power. This paper describes the salient features of this technology node, the process architecture, the device design rationale, and the process design interactions.