ACM Computing Surveys (CSUR)
Overview of the IBM Blue Gene/P project
IBM Journal of Research and Development
Overview of the Blue Gene/L system architecture
IBM Journal of Research and Development
IBM Journal of Research and Development
The IBM Blue Gene/Q interconnection network and message unit
Proceedings of 2011 International Conference for High Performance Computing, Networking, Storage and Analysis
The IBM Blue Gene/Q Compute Chip
IEEE Micro
The IBM Blue Gene/Q Interconnection Fabric
IEEE Micro
Scalable and modular pervasive logic/firmware design
IBM Journal of Research and Development
Packaging the IBM Blue Gene/Q supercomputer
IBM Journal of Research and Development
Design for low power and power management in IBM Blue Gene/Q
IBM Journal of Research and Development
Modeling, validation, and co-design of IBM Blue Gene/Q: tools and examples
IBM Journal of Research and Development
IBM Blue Gene/Q memory subsystem with speculative execution and transactional memory
IBM Journal of Research and Development
Packaging the IBM Blue Gene/Q supercomputer
IBM Journal of Research and Development
IBM Blue Gene/Q system software stack
IBM Journal of Research and Development
Modeling, validation, and co-design of IBM Blue Gene/Q: tools and examples
IBM Journal of Research and Development
11 PFLOP/s simulations of cloud cavitation collapse
SC '13 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis
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The heart of a Blue Gene®/Q system is the Blue Gene/Q Compute (BQC) chip, which combines processors, memory, and communication functions on a single chip. The Blue Gene/Q Compute chip has 16 + 1 + 1 processor cores, each with a quad single-instruction, multiple-data (SIMD) floating-point unit, and a multi-versioned Level 2 cache that provides hardware support for transactional memory, speculative execution, and atomic operations. The Blue Gene/Q Compute chip further contains dual on-chip memory controllers for directly attached DDR3 (double data rate type 3) memory and sophisticated networking logic for chip-to-chip communications.