Transactional memory: architectural support for lock-free data structures
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Removing architectural bottlenecks to the scalability of speculative parallelization
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
HPCA '98 Proceedings of the 4th International Symposium on High-Performance Computer Architecture
Software and Hardware for Exploiting Speculative Parallelism with a Multiprocessor
Software and Hardware for Exploiting Speculative Parallelism with a Multiprocessor
Hardware support for thread-level speculation
Hardware support for thread-level speculation
Tasking with out-of-order spawn in TLS chip multiprocessors: microarchitecture and compilation
Proceedings of the 19th annual international conference on Supercomputing
Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessors
ACM Transactions on Architecture and Code Optimization (TACO)
Overview of the IBM Blue Gene/P project
IBM Journal of Research and Development
Proceedings of the twentieth annual symposium on Parallelism in algorithms and architectures
Blue Gene/L compute chip: memory and Ethernet subsystem
IBM Journal of Research and Development
Design of the IBM Blue Gene/Q compute chip
IBM Journal of Research and Development
IBM Blue Gene/Q system software stack
IBM Journal of Research and Development
Modeling, validation, and co-design of IBM Blue Gene/Q: tools and examples
IBM Journal of Research and Development
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The memory subsystem of the IBM Blue Gene®/Q Compute chip features multi-versioning and access conflict detection. Its ordered and unordered transaction modes implement both speculative execution (SE) and transactional memory (TM). Blue Gene/Q's large shared second-level cache serves as storage for speculative versions, allowing up to 30 MB of speculative state for the 64 threads of a Blue Gene/Q node, which in the extreme can be associated with a single large transaction. Using the shared access to speculative data, the SE model implements forwarding, allowing data produced by one thread to be accessed by another thread while both are still speculative. This paper presents an overview of Blue Gene/Q's approach to TM and SE: the memory subsystem hardware and operating system extensions, IBM XL compiler support via OpenMP® extensions, and a cost estimation model for executing code speculatively. The model is validated using synthetic benchmarks.