Intrinsic evolvable hardware for combinatorial synthesis based on SoC+FPGA and GPU platforms

Authors:
Carlos Iván Camargo Bareño;Cesar Augusto Pedraza Bonilla;Luis Fernado Niño;José Ignacio Martinez Torre
Affiliations:
Universidad Nacional de Colombia, Bogotá, Colombia;Universidad Santo Tomás de Aquino, Bogotá, Colombia;Universidad Nacional de Colombia, Bogotá, Colombia;Universidad Rey Juan Carlos, Madrid, Spain
Venue:
Proceedings of the 13th annual conference companion on Genetic and evolutionary computation
Year:
2011

Citing 2
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Abstract

This paper presents a novel a parallel genetic programming (PGP) boolean synthesis implementation on a low cost cluster of an embedded open platform called SIE. Some tasks of the PGP have been accelerated through a hardware coprocessor called FCU, that allows to evaluate individuals onchip as intrinsic evolution. Results have been compared with GPU and HPC implementations, resulting in speedup values up to approximately 2 and 180 respectively.