Theoretical Computer Science
Systematic Formal Verification for Fault-Tolerant Time-Triggered Algorithms
IEEE Transactions on Software Engineering
PVS: A Prototype Verification System
CADE-11 Proceedings of the 11th International Conference on Automated Deduction: Automated Deduction
ICDCS '02 Proceedings of the 22 nd International Conference on Distributed Computing Systems (ICDCS'02)
Timing-sync protocol for sensor networks
Proceedings of the 1st international conference on Embedded networked sensor systems
The flooding time synchronization protocol
SenSys '04 Proceedings of the 2nd international conference on Embedded networked sensor systems
Modeling Time-Triggered Protocols and Verifying Their Real-Time Schedules
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
Tight bounds for clock synchronization
Proceedings of the 28th ACM symposium on Principles of distributed computing
Analysis of a Clock Synchronization Protocol for Wireless Sensor Networks
FM '09 Proceedings of the 2nd World Congress on Formal Methods
Software monitoring with controllable overhead
International Journal on Software Tools for Technology Transfer (STTT) - Runtime Verification
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We use the Uppaal model checker for timed automata to verify the Timing-Sync time-synchronization protocol for sensor networks (TPSN), the clock-synchronization algorithm of Lenzen, Locher and Wattenhofer (LLW) for general distributed systems, and the clock-thread technique of the software monitoring with controllable overhead algorithm (SMCO). Clock-synchronization algorithms such as TPSN, LLW, and SMCO must be able to perform arithmetic on clock values to calculate clock drift and network propagation delays. They must also be able to read the value of a local clock and assign it to another local clock. Such operations are not directly supported by the theory of timed automata. To overcome this formal-modeling obstacle, we augment the Uppaal specification language with the integer clock-derived type. Integer clocks, which are essentially integer variables that are periodically incremented by a global pulse generator, greatly facilitate the encoding of the operations required to synchronize clocks as in the TPSN, LLW, and SMCO protocols. With these integer-clock-based models in hand, we use Uppaal to verify a number of key correctness properties, including network-wide time synchronization, bounded clock skew, bounded overhead skew, and absence of deadlock. We also use the Uppaal Tracer tool to illustrate how integer clocks can be used to capture clock drift and resynchronization during protocol execution.