Automatic generation of compiled simulations through program specialization
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Ravel: assigned-delay compiled-code logic simulation
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Parallel logic simulation of VLSI systems
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Introduction to Computing Systems: From Bits & Gates to C & Beyond
Introduction to Computing Systems: From Bits & Gates to C & Beyond
Compiled code in distributed logic simulation
Proceedings of the 38th conference on Winter simulation
The inversion algorithm for digital simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A hierarchical compiled code event-driven logic simulator
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Simulating digital circuits with one bit per wire
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Digital hardware designs are nearly always tested and validated prior to deployment using functional-level simulation. Each component of the design, such as a four-bit adder or an eight-to-one multiplexer, is described and modeled as a set of inputs and a set of outputs that change based on changes in the input. Using traditional discrete event simulation, each change in the input set for a component would result in future events being scheduled for each input connected to the component's output. These future events would represent the changed inputs and speed-of-light delays between an output and the corresponding input. Further, some components might respond to clock-tick events that allow for synchronous actions, such as the latching of a bit in a single flip-flop, which results in a changed output only during a specific clock event. We discuss a different approach to functional-level modeling that we call the Pull-Model. In this approach, components do not schedule events to notify other components of input data changes. Rather, each component queries other components asking for the current output value, and does so only when the value is actually needed to model the data flow at that time. We show that this approach significantly reduces the number of events, even when modeling a very simple CPU architecture with only a few components.