A 1.2v 55mW 12bits self-calibrated dual-residue analog to digital converter in 90 nm CMOs

  • Authors:

  • Amir Zjajo;Jose Pineda de Gyvez

  • Affiliations:

  • Delft University of Technology, Delft, Netherlands;Eindhoven University of Technology, Eindhoven, Netherlands

  • Venue:
  • Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
  • Year:
  • 2011

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Abstract

This paper reports design, optimization, efficiency and measurement results of the 12 bits dual-residue multi-step A/D converter. The calibration procedure based on the steepest-descent estimation method is enhanced with dedicated embedded sensors, which register on-chip process parameter and temperature variations. The prototype A/D converter with performance of 68.6 dB SNDR, 70.3 dB SNR, 78.1 dB SFDR, 11.1 ENOB at 60 MS/s has been fabricated in standard single poly, six metal 90 nm CMOS, consumes only 55 mW and measures 0.75 mm2. The on-chip calibration logic occupies an area of 0.14 mm2 and consumes 11 mW of power.