A low-power direct digital frequency synthesizer using an analogue-sine-conversion technique

  • Authors:

  • Jun-Hong Weng;Ching-Yuan Yang;Yi-Lin Jhu

  • Affiliations:

  • National Chung Hsing University, Taichung, Taiwan Roc;National Chung Hsing University, Taichung, Taiwan Roc;National Chung Hsing University, Taichung, Taiwan Roc

  • Venue:
  • Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
  • Year:
  • 2011

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Abstract

A new approach for direct digital frequency synthesizer (DDFS) with analogue sine conversion is presented. The proposed DDFS adopts the ROM-less architecture with linear DAC to achieve higher speed operation and lower power consumption. Fabricated by 0.18-um CMOS process, the DDFS employs a 9-bits pipeline accumulator to provide an 8-bits amplitude resolution for the DAC circuit. At 1-GHz clock frequency, the power consumption is 50 mw at 1.8-V power supply and the spurious free dynamic range (SFDR) is 44 dBc at the Nyquist synthesized frequency. The total chip area is 0.52 mm2.