Learning Patterns of Activity Using Real-Time Tracking
IEEE Transactions on Pattern Analysis and Machine Intelligence
Imagine: Media Processing with Streams
IEEE Micro
User-Level DMA without Operating System Kernel Modification
HPCA '97 Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture
ROS-DMA: A DMA Double Buffering Method for Embedded Image Processing with Resource Optimized Slicing
RTAS '06 Proceedings of the 12th IEEE Real-Time and Embedded Technology and Applications Symposium
DMA Performance Analysis and Multi-core Memory Optimization for SWIM Benchmark on the Cell Processor
ISPA '08 Proceedings of the 2008 IEEE International Symposium on Parallel and Distributed Processing with Applications
Lightweight DMA management mechanisms for multiprocessors on FPGA
ASAP '08 Proceedings of the 2008 International Conference on Application-Specific Systems, Architectures and Processors
Real-Time Adaptive Background Modeling for Multicore Embedded Systems
Journal of Signal Processing Systems
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The emergence of multicore platforms has tremendous potential for achieving real-time performance of complex computer vision algorithms. However, these applications must run on embedded, mobile platforms with stringent size weight, power, and cost constraints. High utilization of local storage on execution cores and low-latency, highbandwidth data transfers between this storage and main memory are critical for real-time mobile system performance. General purpose processors employ hardware techniques, such as high-speed bus architecture and efficient data arbitration schemes, to address the memory bandwidth gap. However, these techniques are insufficient for mobile systems requirements. Concurrent algorithmic and architectural optimizations are necessary. This paper uses concurrency to minimize data transfer latency when executing video surveillance algorithms on multicore embedded architectures. It introduces cat-tail DMA, a technique that provides low-overhead, globally-ordered, nonblocking DMA transfers. Using this technique, data transfer latencies are reduced by over 30% for background modeling applications, while the local core storage utilization is increased by 60% over existing techniques.