An AER spike-processing filter simulator and automatic VHDL generator based on cellular automata

Authors:
Manuel Rivas-Perez;A. Linares-Barranco;Francisco Gomez-Rodriguez;A. Morgado;A. Civit;G. Jimenez
Affiliations:
Robotic and Technology of Computers Lab. University of Seville. Spain;Robotic and Technology of Computers Lab. University of Seville. Spain;Robotic and Technology of Computers Lab. University of Seville. Spain;Computer Architecture and Technology Area, University of Cadiz. Spain;Robotic and Technology of Computers Lab. University of Seville. Spain;Robotic and Technology of Computers Lab. University of Seville. Spain
Venue:
IWANN'11 Proceedings of the 11th international conference on Artificial neural networks conference on Advances in computational intelligence - Volume Part I
Year:
2011

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Abstract

Spike-based systems are neuro-inspired circuits implementations traditionally used for sensory systems or sensor signal processing. Address-Event-Representation (AER) is a neuromorphic communication protocol for transferring asynchronous events between VLSI spike-based chips. These neuroinspired implementations allow developing complex, multilayer, multichip neuromorphic systems and have been used to design sensor chips, such as retinas and cochlea, processing chips, e.g. filters, and learning chips. Furthermore, Cellular Automata (CA) is a bio-inspired processing model for problem solving. This approach divides the processing synchronous cells which change their states at the same time in order to get the solution. This paper presents a software simulator able to gather several spike-based elements into the same workspace in order to test a CA architecture based on AER before a hardware implementation. Furthermore this simulator produces VHDL for testing the AER-CA into the FPGA of the USBAER AER-tool.