How GPUs can outperform ASICs for fast LDPC decoding
Proceedings of the 23rd international conference on Supercomputing
High-throughput layered LDPC decoding architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Speed Improves Delay-Capacity Trade-Off in MotionCast
IEEE Transactions on Parallel and Distributed Systems
Delay and capacity tradeoff analysis for motioncast
IEEE/ACM Transactions on Networking (TON)
Good error-correcting codes based on very sparse matrices
IEEE Transactions on Information Theory
Design of capacity-approaching irregular low-density parity-check codes
IEEE Transactions on Information Theory
Regular and irregular progressive edge-growth tanner graphs
IEEE Transactions on Information Theory
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In this paper, a novel and systematic LDPC codeword construction and verification methodology is proposed. The methodology is composed by the simulated annealing based LDPC codeword constructor, the GPU based high-speed codeword selector and the ant colony optimization based pipeline scheduler. Compared to the traditional ways, this methodology enables us to construct both decoding-performance-aware and hardware-efficiency-aware LDPC codewords in a short time. Simulation results show that the generated codewords have much less cycles (length 6 cycles eliminated) and memory conflicts (75% reduction on idle clocks), while having noBER performance loss compared to WiMAXcodewords. Additionally, the simulation speeds up by 490 times under float precision against CPU and a net throughput 24.5Mbps is achieved.