Massive parallel LDPC decoding on GPU
Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming
How GPUs can outperform ASICs for fast LDPC decoding
Proceedings of the 23rd international conference on Supercomputing
Key technologies for next-generation terrestrial digital television standard DVB-T2
IEEE Communications Magazine
Massively LDPC Decoding on Multicore Architectures
IEEE Transactions on Parallel and Distributed Systems
A Scalable LDPC Decoder on GPU
VLSID '11 Proceedings of the 2011 24th International Conference on VLSI Design
Implementation and performance analysis of DVB-T2 rotated constellation demappers on a GPU
Analog Integrated Circuits and Signal Processing
CuSora: Real-time software radio using multi-core graphics processing unit
Journal of Systems Architecture: the EUROMICRO Journal
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The second generation terrestrial TV broadcasting standard from the digital video broadcasting (DVB) project, DVB-T2, has recently been standardized. In this article we perform a complexity analysis of our software defined implementation of the modulator/demodulator parts of a DVB-T2 transmitter and receiver. First we describe the various stages of a DVB-T2 modulator and demodulator, as well as how they have been implemented in our system. We then perform an analysis of the computational complexity of each signal processing block. The complexity analysis is performed in order to identify the blocks that are not feasible to run in realtime on a general purpose processor. Furthermore, we discuss implementing these computationally heavy blocks on other architectures, such as GPUs (graphics processing units) and FPGAs (field-programmable gate arrays), that would still allow them to be implemented in software and thus be easily reconfigurable.