Validating system requirements by functional decomposition and dynamic analysis
ICSE '89 Proceedings of the 11th international conference on Software engineering
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Proceedings of the 39th annual Design Automation Conference
Concurrent and Real Time Systems: The CSP Approach
Concurrent and Real Time Systems: The CSP Approach
Standards for Local Area Networks: Carrier Sense Multiple Access with Collision Detection (Csma-CD) Access Method and Physical Layer Specifications - Standards 802.3
Case Study: Specification and Refinement of the PI-Bus
FME '94 Proceedings of the Second International Symposium of Formal Methods Europe on Industrial Benefit of Formal Methods
A refinement approach to design and verification of on-chip communication protocols
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Understanding Concurrent Systems
Understanding Concurrent Systems
Principles of Asynchronous Circuit Design: A Systems Perspective
Principles of Asynchronous Circuit Design: A Systems Perspective
Measuring the Gap Between FPGAs and ASICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper we present a Design-for-Verification framework for a Configurable Performance-Critical Communication Interface. To manage the inherent complexity of the problem we decomposed the interface into independent parametrisable communication blocks. Tock-CSP was then used to model the timing and functional specifications of our interface. The FDR model checker and its tau-priority model were used to prove that the properties of the configured interface are within the properties of targeted communication protocols.