Communications of the ACM - Special issue on parallelism
Pseudo MIMD array processor—AAP2
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Computer
IEEE Transactions on Pattern Analysis and Machine Intelligence - Special Issue on Industrial Machine Vision and Computer Vision Technology:8MPart
The AIS-5000 Parallel Processor
IEEE Transactions on Pattern Analysis and Machine Intelligence - Special Issue on Industrial Machine Vision and Computer Vision Technology:8MPart
Program optimization for instruction caches
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
Scans as Primitive Parallel Operations
IEEE Transactions on Computers
An analysis of instruction-cached SIMD computer architecture
An analysis of instruction-cached SIMD computer architecture
Operating System Elements: A User Perspective
Operating System Elements: A User Perspective
The Logical Design of Operating Systems
The Logical Design of Operating Systems
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SIMD instruction cache (or I-cache) is proposed to remedy a heretofore un-compensated instruction delivery rate limitation of SIMD computers. This paper introduces the concept of SIMD I-cache and sketches the I-cache design space. On the basis of throughput using chip area as a hardware cost constraint, detailed evaluations of simple I-cache variants for a diverse set of sample problems are presented. Simple I-cache variants occupy negligible area in chips while providing significant speedups, even for problems ordinarily thought to be inherently communication-bound. These results suggest that I-cached SIMD computers exhibit the highest throughput of any multiprocessors for scalable data-parallel problems.