Flexible LDPC decoder architectures
VLSI Design - Special issue on Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation
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This paper presents a bottom up approach for implementing high throughput, scalable, layered LDPC decoding architecture for multi-standard applications. A generic implementation of fully parallel check node along with a block level Channel Memory organization scheme are two elements of novelty of this work. The proposed decoder IP core is synthesizable for all codes defined by WiMAX (WiFi) standards. Synthesis results are presented based on 130 nm standard cell ASIC technology.