A code generation method for system-level synthesis on ASIC, FPGA and manycore CGRA
Proceedings of the First International Workshop on Many-core Embedded Systems
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We have proposed a Dynamically Reconfigurable Resource Array (DRRA), which is a Coarse Grain Reconfigurable Architecture (CGRA). In this paper, we propose a hierarchical method for compiling DSP applications in Simulink into DRRA. In this method, each function in DRRA library can be implemented in different architecture styles and also each architectural style can be implemented in varying degrees of parallelism. Since selecting an appropriate implementation for functions of an application is very effective in performance and cost of architecture, we also formulate an optimization problem that considers implementations of functions as decision variables in order to minimize total energy consumed in the architecture under performance and cost constraints. A realistic case study exhibits up to 89% reduction of total energy consumption. It is worth mentioning that by using the proposed hierarchically compilation method, the design space is reduced dramatically while keeping the solution optimized in term of energy consumption. Hence, the optimization algorithm has low run-time complexity, enabling quick exploration of large design spaces.