SystemC: a modeling platform supporting multiple design abstractions
Proceedings of the 14th international symposium on Systems synthesis
Compilers: Principles, Techniques, and Tools (2nd Edition)
Compilers: Principles, Techniques, and Tools (2nd Edition)
SBAC-PAD '10 Proceedings of the 2010 22nd International Symposium on Computer Architecture and High Performance Computing
A Library Development Framework for a Coarse Grain Reconfigurable Architecture
VLSID '11 Proceedings of the 2011 24th International Conference on VLSI Design
DSD '11 Proceedings of the 2011 14th Euromicro Conference on Digital System Design
Address generation scheme for a coarse grain reconfigurable architecture
ASAP '11 Proceedings of the ASAP 2011 - 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors
Global Control and Storage Synthesis for a System Level Synthesis Approach
FCCM '13 Proceedings of the 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines
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This paper presents a code generation method that translates an intermediate Register-Transfer Level (RTL) model of a system into its corresponding VHDL code for ASIC and FPGAs and MATLAB functions for manycores CGRAs. The intermediate representation consists of Function Implementation (FIMPs) and the glue logic. FIMPs are VHDL design units for the ASIC and FPGA implementation styles and MATLAB function templates for the CGRA implementation style, while the glue logic is a compact data structure storing Global Interconnect and Control (GLIC) information. The automatically generated implementation codes increase the resource usage by 1.5% on the average while reducing total design effort by two orders of magnitudes.