A code generation method for system-level synthesis on ASIC, FPGA and manycore CGRA
Proceedings of the First International Workshop on Many-core Embedded Systems
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SYLVA is a System Level Architectural Synthesis Framework that translates Synchronous Data Flow (SDF) models of DSP sub-systems like modems and codecs into hardware implementation in ASIC/Standard Cells, FPGAs or CGRAs (Coarse Grain Reconfigurable Fabric).