A 100 GOPS ASP based baseband processor for wireless communication
Proceedings of the Conference on Design, Automation and Test in Europe
A code generation method for system-level synthesis on ASIC, FPGA and manycore CGRA
Proceedings of the First International Workshop on Many-core Embedded Systems
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In this paper, we describe a versatile address generation scheme for distributed storage resources of a coarse grain Parallel Distributed Digital Signal Processing (PDDSP) reconfigurable architecture under development in our group. This scheme proposes the distributed address generation units (AGUs) to decouple the address generation logic with compute logic to exploit parallelism (ILP and TLP). To achieve this, the proposed distributed address generation scheme with standard DSP address generation modes like linear vectorized, circular buffer and bit-reverse addressing, all with parameterizable address range and increment/decrement offsets is further enhanced with temporal flexibility by introducing three dynamically programmable delays: initial delay before the stream starts, middle delay after every address generation for the stream and end delay after the stream is complete. The dynamic programmability of these delays makes streams elastic that can be chained with an interrupt mechanism to create chained-elastic streams. Our approach is compared with the traditional approach of using VLIW and Scalar. Our approach shows 21脳 (Scalar), 10脳(VLIW) reduction in instructions and 2脳(Scalar) reduction in cycles for a single thread FIR filter. When compared for Synchronous and Asynchronous scenarios of two parallel treads T1 and T2, our approach shows 4.6脳(Scalar), 5.6脳(VLIW) reduction in instructions, 1.76脳 reduction in cycles for Synchronous and 4.6脳(Scalar), 15脳(VLIW) reduction in instructions, 1.76脳(Scalar) reduction in cycles for Asynchronous threads.