Towards a generic verification methodology for system models
Proceedings of the Conference on Design, Automation and Test in Europe
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A key challenge in software development process is to detect errors in earlier phases of the software life cycle. For this purpose, the verification of UML diagrams plays an important role in detecting flaws at the analysis and design phase. To enhance the correctness of one of the most popular UML diagrams: sequence diagram (SD), model checking propositional projection temporal logic (PPTL) is adopted. With this method, event deterministic finite automata are used to describe the formal models of an SD, and PPTL is selected to describe a desired property. Experimental result shows that the proposed approach is useful for verifying the properties of SDs and hence for improving the correctness of SDs.