Fast Path Performance of Packet Cache Router Using Multi-core Network Processor

Authors:
Shu Yamamoto;Akihiro Nakao
Affiliations:
-;-
Venue:
Proceedings of the 2011 ACM/IEEE Seventh Symposium on Architectures for Networking and Communications Systems
Year:
2011

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Abstract

The packet cache router enabling the packet-level redundant data elimination is effective to reduce the P2P swarm traffic traversing ISP inter-domain links. To deploy the packet cache router in the ISP networks, the high performance packet processing is required. In this paper, we implement a packet cache router by a multi-core network processor using fast path/slow path application structure and evaluate its performance.