Time-parallel simulation of cascaded statistical multiplexers

  • Authors:

  • Ioanis Nikolaidis;Richard Fujimoto;C. Anthony Cooper

  • Affiliations:

  • College of Computing Georgia Institute of Technology Atlanta, GA;College of Computing Georgia Institute of Technology Atlanta, GA;Bellcore, NVC-1H225, 331 Newman Springs Rd., Red Bank, NJ

  • Venue:
  • SIGMETRICS '94 Proceedings of the 1994 ACM SIGMETRICS conference on Measurement and modeling of computer systems
  • Year:
  • 1994

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Abstract

The multiplexing of several lightly loaded links onto a more heavily loaded output link is a problem of considerable importance to the design and traffic engineering of many types of packet-oriented telecommunications equipment, including that used in Asynchronous Transfer Mode (ATM) networks. Network configurations generally require the cascaded operation of such multiplexers and switches. Important objectives to achieve small cell loss ratios while maintaining efficient utilization of the transmission links. The small cell loss ratio objective results in extremely long simulation runs. To address this problem, we propose a new technique that relies on a compact description for the arriving/departing traffic at the multiplexers and a time-parallel scheme without fix-up phases for effective parallelization. The technique does not make assumptions about the analytical nature of the arrival process, thereby allowing trace-driven simulations to be performed as well. We demonstrate the method for a number of configurations and traffic scenarios, and observe that it yields one to two orders of magnitude speedup on a 32 processor Kendall Square Research KSR-1 multiprocessor compared to an efficient cell-level simulation executing on a Sparc-10 workstation.