Linearizability: a correctness condition for concurrent objects
ACM Transactions on Programming Languages and Systems (TOPLAS)
A methodology for implementing highly concurrent data objects
ACM Transactions on Programming Languages and Systems (TOPLAS)
A method for implementing lock-free shared-data structures
SPAA '93 Proceedings of the fifth annual ACM symposium on Parallel algorithms and architectures
The C++ Programming Language
High performance dynamic lock-free hash tables and list-based sets
Proceedings of the fourteenth annual ACM symposium on Parallel algorithms and architectures
Introduction to Algorithms
A Pragmatic Implementation of Non-blocking Linked-Lists
DISC '01 Proceedings of the 15th International Conference on Distributed Computing
A Practical Multi-word Compare-and-Swap Operation
DISC '02 Proceedings of the 16th International Conference on Distributed Computing
Even Better DCAS-Based Concurrent Deques
DISC '00 Proceedings of the 14th International Conference on Distributed Computing
Split-ordered lists: lock-free extensible hash tables
Proceedings of the twenty-second annual symposium on Principles of distributed computing
Correction of a Memory Management Method for Lock-Free Data Structures
Correction of a Memory Management Method for Lock-Free Data Structures
Hazard Pointers: Safe Memory Reclamation for Lock-Free Objects
IEEE Transactions on Parallel and Distributed Systems
Scalable lock-free dynamic memory allocation
Proceedings of the ACM SIGPLAN 2004 conference on Programming language design and implementation
A scalable lock-free stack algorithm
Proceedings of the sixteenth annual ACM symposium on Parallelism in algorithms and architectures
Nonblocking memory management support for dynamic-sized data structures
ACM Transactions on Computer Systems (TOCS)
Bridging the Gap between Systems Design
SEW '05 Proceedings of the 29th Annual IEEE/NASA on Software Engineering Workshop
STAPL: an adaptive, generic parallel C++ library
LCPC'01 Proceedings of the 14th international conference on Languages and compilers for parallel computing
Allocating memory in a lock-free manner
ESA'05 Proceedings of the 13th annual European conference on Algorithms
Lock-free and practical doubly linked list-based deques using single-word compare-and-swap
OPODIS'04 Proceedings of the 8th international conference on Principles of Distributed Systems
Associative Parallel Containers in STAPL
Languages and Compilers for Parallel Computing
Verification and semantic parallelization of goal-driven autonomous software
Autonomics '08 Proceedings of the 2nd International Conference on Autonomic Computing and Communication Systems
Non-blocking Array-Based Algorithms for Stacks and Queues
ICDCN '09 Proceedings of the 10th International Conference on Distributed Computing and Networking
NOBLE: non-blocking programming support via lock-free shared abstract data types
ACM SIGARCH Computer Architecture News
Scalable nonblocking concurrent objects for mission critical code
Proceedings of the 24th ACM SIGPLAN conference companion on Object oriented programming systems languages and applications
A scalable lock-free stack algorithm
Journal of Parallel and Distributed Computing
Effective use of non-blocking data structures in a deduplication application
Proceedings of the 2013 companion publication for conference on Systems, programming, & applications: software for humanity
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We present a first lock-free design and implementation of a dynamically resizable array (vector). The most extensively used container in the C++ Standard Template Library (STL) is vector, offering a combination of dynamic memory management and constant-time random access. Our approach is based on a single 32-bit word atomic compare-and-swap (CAS) instruction. It provides a linearizable and highly parallelizable STL-like interface, lock-free memory allocation and management, and fast execution. Our current implementation is designed to be most efficient on multi-core architectures. Experiments on a dual-core Intel processor with shared L2 cache indicate that our lock-free vector outperforms its lock-based STL counterpart and the latest concurrent vector implementation provided by Intel by a large factor. The performance evaluation on a quad dual-core AMD system with non-shared L2 cache demonstrated timing results comparable to the best available lock-based techniques. The presented design implements the most common STL vector's interfaces, namely random access read and write, tail insertion and deletion, pre-allocation of memory, and query of the container's size. Using the current implementation, a user has to avoid one particular ABA problem.